Manufacturers of semiconductor memory devices, particularly dynamic random access memory (DRAM), continue to pursue higher speed operation and, as a result, synchronous DRAM has been introduced. The synchronous DRAM operates synchronously with a is system clock provided from outside of the chip, and particularly, a typical operation of the synchronous DRAM is a burst operation in which when a burst length is set by a mode resist set (MRS) set upon enabling of the synchronous DRAM, data is continuously inputted or outputted by the set burst length by read command and write command.
The burst length set for the burst operation includes 4, 8, 16 and so on. An existing DDR2 SDRAM supports only burst lengths of 4 and 8, and a mobile DDR2 SDRAM supports burst lengths of 4, 8 and 16. Here, the burst length of 8 means that data of 8 bits is continuously inputted or outputted by the read command or the write command.
However, the conventional semiconductor memory device has a problem that, once the burst length is set by the MRS, the data is inputted or outputted by the set burst length regardless of actually inputted or outputted data length. That is to say, when the burst length is set to 8, the burst operation is terminated after the data of 8 bits is all inputted or outputted, even when actually inputted or outputted data is 4 bits. Therefore, unnecessary burst operation period is generated by the operation of inputting or outputting unnecessary data of 4 bits.